1. Field of the Invention
The present invention relates to a driving circuit for a display device, and, a test circuit and a test method for the driving circuits. Specifically, the present invention relates to a driving circuit for a display device for driving a display panel in a voltage range between a high negative voltage and a high positive voltage, and a test circuit and test method for measuring the high negative voltage outputted from the driving circuits.
2. Description of Related Art
For a driving circuit (e.g., a liquid crystal display panel driving IC (Integrated Circuit)), which is used for a display device included in a portable electronic apparatus having a detachable battery, such as a cellular phone and a digital camera, there is a case where a power source voltage is interrupted or the power source voltage abruptly drops because of falling off of the buttery and the like.
FIG. 1 is a diagram showing one example of a conventional configuration of a liquid crystal display panel driver IC 200. The liquid crystal display panel driver IC 200 includes a source driver circuit 11, a gate driver circuit 12, a power source section 14 for the source driver circuit, a power source section 25 for the gate driver circuit, and an afterimage prevention circuit 23. The power source section 14 includes a charge pump circuit 140. The power source section 25 includes charge pump circuits 151 and 252. It is preferable that the liquid crystal display panel driver IC 200 includes the afterimage prevention circuit 23 in order that, when the interruption or the drop of the power source voltage occurs, an image displayed just before such incident may not remain. The afterimage prevention circuit 23 does not render an image displayed immediately before the sudden drop of the power source voltage in the liquid crystal display panel as an afterimage even at the case of the incident, so as to prevent burn-in on the screen and deterioration of a liquid crystal display panel 10.
Techniques related to the afterimage prevention circuit are described, for example, in Japanese Laid-Open Patent Application JP-P 2007-94016A (hereinafter referred to as the Patent Document 1) and JP-P 2005-331927A (hereinafter referred to as the Patent Document 2).
The liquid crystal display panel driver IC 200 includes a power source circuit which generates a driving signal voltage for driving the liquid crystal display panel 10. This power source circuit includes a power source section 25 for a gate driver circuit, which supplies high voltages (a high positive voltage VGH and a high negative voltage VGL) to a gate driver circuit 12 that needs the high voltages. Such a power source circuit needs to be constructed by a high-voltage process that can handle a high negative voltage in particular. For example, the high negative voltage is supplied as a substrate voltage to a charge pump circuit 252 generating a high negative voltage lower than the ground voltage GND.
The afterimage prevention circuit 23 includes an electric charge discharging circuit 230 as shown in FIG. 2. The electric charge discharging circuit 230 includes a switching circuit (e.g., an NMOS transistor MN10) connected between a power source terminal 2 of the ground voltage GND and a terminal 4 for supplying the high negative voltage VGL. The NMOS transistor MN10 controls a connection between the power source terminal 2 and the terminal 4 depending on a level of the control signal Vcon supplied into its gate. For example, when the power source voltage VDC indicates a normal value, the control signal Vcon of a low level is supplied, and the NMOS transistor MN10 becomes an OFF state to isolate the power source terminal 2 and the terminal 4. On the other hand, when the power source voltage VDC indicates an abnormal drop or is interrupted, the control signal Vcon of the high level is supplied, the NMOS transistor MN10 becomes an ON state to connect the power source terminal 2 to the terminal 4. By these operations, the voltage of the terminal 4 varies so as to converge to the ground voltage GND from the high negative voltage VGL, and a transistor (TFT: Thin Film Transistor) of each pixel in the liquid crystal display panel 10 becomes a half-conduction state, namely, a half-ON state. As a result, an impedance of the TFT of each pixel falls and electric charges accumulated in a liquid crystal capacity is discharged. Thereby the afterimage can be prevented.
The charge pump circuit 252 also includes the electric charge discharging circuit 230 as shown in FIG. 2. The charge pump circuit 252 changes its operational mode based on the supplied control signal Vcon. For example, it is turned to an OFF state (the output voltage is 0 V (the ground voltage GND)) in response to a high-level control signal Vcon, and is turned to an ON (operation) state (the output voltage is the high negative voltage VGL) in response to a low-level control signal Vcon. In detail, when the low level control signal Vcon is supplied, the NMOS transistor MN10 becomes the OFF state to isolate the power source terminal 2 and the terminal 4 (operation state). On the other hand, when the high-level control signal Vcon is supplied, the NMOS transistor MN10 becomes an ON state to connect the power source terminal 2 to the terminal 4 (OFF state). Thereby, the voltage of the terminal 4 changes so as to converge to the ground voltage GND from the high negative voltage VGL. Here, the electric charge discharging circuit 230 provided in the afterimage prevention circuit 23 and the electric charge discharging circuit 230 provided in the charge pump circuit 252 are different from each other.
Since the liquid crystal display panel driver IC 200 requires the power source section 25 for the gate driver circuit for outputting the high positive voltage VGH and the high negative voltage VGL, the circuit needs to be constructed by a high-voltage process, especially by a process that can handle the high negative voltage. Moreover, in the case where elements are isolated only by a PN junction isolation and a substrate of the IC chip is a P-type substrate, the substrate voltage must be a lowest voltage on the chip. In this case, the high negative voltage VGL is supplied as a substrate voltage of the liquid crystal display panel driver IC 200.
We have now discovered the following facts.
The markets of cellular phones, digital cameras and the like have been expanding, their prices have declined, and therefore the liquid crystal display panel driver IC is in a situation where cost reduction is needed as much as possible. Consequently, it is desired to reduce a test cost as well as reduction in chip sizes and manufacturing costs.
As a test method for reducing the test cost, there is a multi-measurement method in which a plurality of chips (e.g., a plurality of liquid crystal display panel drivers IC 200) is tested simultaneously. The multi-measurement method is a method that shortens a test time per chip to reduce the test cost by performing simultaneous probing on a plurality of chips on one wafer and making a test simultaneously or sequentially.
It becomes important to devise a circuit configuration that enables the test cost to be reduced also for the liquid crystal display panel driver IC 200, which includes addition functions such as the afterimage prevention circuit 23, and circuits such as a high negative power source (e.g., the charge pump circuit 252). At the same time, it becomes also important to perform a more stable test.
Here, a plurality of IC chips that is probed simultaneously is called DUT (Device Under Test). Since a substrate (not illustrated) of the each of the IC chips of the DUT is common as a wafer substrate, their electric potentials become equal to each other. Moreover, a minimum voltage in the IC chip (in the above-mentioned example, the high negative voltage VGL) must be supplied to the substrate (semiconductor substrate) of the IC chips produced on the wafer substrate of a P-type semiconductor. As a result, the VGL terminals (in the above-mentioned example, the terminals 4) of all the IC chips in the DUT will be electrically connected together to each other form the substrate of each IC chip via the wafer substrate.
An ground terminal (GND1) being set in an IC tester is connected to the ground terminal (GND) in each of the IC chips in the DUT. However, usually a switch or the like is not provided between the ground terminals (GND) of respective IC chips in the DUT in order to lower source impedance at the time of the test. Therefore, the ground terminals (GND) of all the IC chips of the DUT will be commonly connected to the ground voltage (GND).
Referring to FIG. 3, the conventional multi-measurement method for the liquid crystal display panel driver IC 200 will be explained in detail. Here, in this multi-measurement method, the two liquid crystal display panel driver ICs 200-1, 200-2 are tested as the DUT. Incidentally, a configuration of each of the liquid crystal display panel driver ICs 200-1, 200-2 is the same as that of the liquid crystal display panel driver IC 200 shown in FIG. 1.
In the liquid crystal display panel driver ICs 200-1, 200-2 in each of which the power source section 25 for the gate driver circuit is provided, the high negative voltage VGL is the substrate voltage for reasons of the process. The substrates (the terminals 4) of the liquid crystal display panel driver ICs 200-1, 200-2 in the DUT are electrically connected to each other via the wafer substrate. Consequently, upon measuring the high negative voltage VGL of each of the liquid crystal display panel driver ICs 200-1, 200-2, in order to eliminate mutual interference, not simultaneous measurement but sequential measurement must be performed also in the multi-measurement.
Here, the measurement of the high negative voltage VGL will be explained in the case where the electric charge discharging circuit 230 shown in FIG. 2 is mounted on the afterimage prevention circuit 23 of the liquid crystal display panel driver IC 200-1 (200-2). When the measurement of the high negative voltage VGL is performed on the liquid crystal display panel driver IC 200-1, the measurement is not performed on the liquid crystal display panel driver IC 200-2. At this time, neither the power source voltage VDC nor the power source voltage of the other system is supplied to the liquid crystal display panel driver IC 200-2. However, in the state where the power source voltage VDC is not supplied, since the high positive voltage VGH is equal to the ground voltage GND, the electric charge discharging circuit 230 operates when the high negative voltage VGL is supplied. At this time, the NMOS transistor MN10 in the electric charge discharging circuit 230 in the afterimage prevention circuit 23 becomes the ON state in response to interruption of the power source voltage VDC, and connects the power source terminal 2 to the terminal 4 in the liquid crystal display panel driver IC 200-2. Consequently, when neither the power source voltage VDC nor the power source voltage of the other system is supplied to the liquid crystal display panel driver IC 200-2, the built-in afterimage prevention circuit 23 (the electric charge discharging circuit 230) connects the power source terminal 2 to the terminal 4.
In this situation, when inspection and measurement of the liquid crystal display panel driver IC 200-1 are started, the high negative voltage VGL begins to drop and a negative voltage is generated by the charge pump circuit 252 of the liquid crystal display panel driver IC 200-1 being activated. At this time, the NMOS transistors MN10 in the electric charge discharging circuits 230 provided in the afterimage prevention circuit 23 and the charge pump circuit 252, respectively, are in the OFF state. However, the ground terminal 2 of the ground voltage GND and the terminal 4 supplied with the high negative voltage VGL are connected by the liquid crystal display panel driver IC 200-2. Therefore, as shown in FIG. 3, an overcurrent flows along a following path: the ground terminal 2, the NMOS transistor MN10 for discharging electric charges in the liquid crystal display panel driver IC 200-2, the substrate (the terminal 4) of the liquid crystal display panel driver IC 200-2, the wafer substrate common to the IC chips (the liquid crystal display panel driver ICs 200-1, 200-2), and the substrate (the terminal 4) of the liquid crystal display panel driver IC 200-1. This current is a load current that flows into the terminal 4 in the liquid crystal display panel driver IC 200-1. This phenomenon makes long a rise time of the high negative voltage VGL by the liquid crystal display panel driver IC 200-1 (a starting time of the liquid crystal display panel driver IC 200-1), and consequently a time until the inspection and measurement of the high negative voltage VGL becomes possible will be lengthened. As described above, if the multi-measurement is performed on the liquid crystal display panel driver IC on which the electric charge discharging circuit 230 is mounted, there will arise a trouble that the test time becomes long. Moreover, in the worst case, it could be possible that the latch-up or the like occur in the liquid crystal display panel driver IC 200-1 by the overcurrent from the liquid crystal display panel driver IC 200-2 which is not an object for the inspection and measurements which makes it impossible to perform the inspection and measurement.
The inspection and measurement of the high negative voltage VGL will be explained in the case where the electric charge discharging circuit 230 shown in FIG. 2 is mounted on the charge pump circuit 252 of the liquid crystal display panel driver ICs 200-1, 200-2. Similarly as described above, in the case where the inspection and the measurement are performed to the high negative voltage VGL of the liquid crystal display panel driver IC 200-1, supply of the power source voltage VDC etc. to the liquid crystal display panel driver IC 200-2 is interrupted. In this case, the control signal Vcon supplied into the electric charge discharging circuit 230 in the liquid crystal display panel driver IC 200-1 is an intermediate potential (an intermediate potential between about 0 V and the high negative voltage VGL). When the inspection (measurement) of the liquid crystal display panel driver IC 200-1 is started and the high negative voltage VGL falls, upon this event, the NMOS transistor MN10 becomes the ON state to connect the ground terminal 2 to the terminal 4. By this mechanism, the overcurrent flows into the terminal 4 of the liquid crystal display panel driver IC 200-1 via the same path as described above. Therefore, even in the case where the electric charge discharging circuit 230 is mounted on the charge pump 252 for generating the high negative voltage VGL, troubles, such as maximization of the test time or occurrence of latch-up, arise similarly as described above.